* Four e500mc Power Architecture cores, each with a backside 128 KB L2 cache with ECC
  – Three levels of instructions: User, supervisor, and hyperviso.

This chip can be used for combined control, data path, and application layer processing in routers, switches, base stat.

P30

P3000AA61L

P3002AA

P3002AB

P3002AC

P3002ACMC

P3002CAL

P3002CBL

P3002GALRP

P3002GBLRP

P3002SALRP

P3002SBLRP

P3002SCLRP

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